The ultimate goal for power electronics is to convert one form of raw electrical energy into a usable power source with the lowest amount of loss. A considerable portion of these losses are due to the use of switching devices themselves. Device losses can be apportioned to conduction loss and switching loss. It is commonly known and practiced that conduction loss can be reduced by driving MOSFETs and IGBTs harder with gate voltages closer to the maximum rating. This lowers the voltage across the device in the path of the amplified current and ultimately reduces power dissipated by the device. However, switching losses of these devices are not as easily characterized or intuitive for power electronics designers. This is mainly due to the fact that the parasitic reactive elements are nonlinear and not as readily documented as I-V characteristics of a given power device. For example, non-linear parasitic capacitances in the device are given for a fixed frequency across a voltage sweep. Parasitic inductance is typically not even mentioned in the datasheet.
The switching losses of these devices depend on these mysterious reactances. A functional way to obtain estimates of switching loss is to test the device under the conditions the device will be used. However, this task must be approached carefully in order to accurately measure the voltage and current of the device. Measurement devices also have parasitic impedances of their own that can add or subtract to switching energy during turn on or turn off and create misleading results. Preliminary testing was performed on multiple devices. After preliminary testing and deliberation, a device-measurement printed circuit board was made to easily replace switching devices of the same package.
This thesis presents switching loss measurements of medium-power capable devices in the tens of kW range. It also aims to attribute characteristics of switching voltage and current waveforms to the internal structure of the devices. The device tester designed is versatile since the output buffer of the gate drive is comprised of D-PAK totem pole BJTs. This is able to drive both current and voltage driven devices, i.e. SiC J-FETs (current-driven) and other voltage-driven devices (i.e. MOSFETs and IGBTs). It also allows for TO-220 and TO-247 packaged power diodes. / Master of Science
| Identifer | oai:union.ndltd.org:VTETD/oai:vtechworks.lib.vt.edu:10919/34568 |
| Date | 09 September 2011 |
| Creators | Kim, Alexander |
| Contributors | Electrical and Computer Engineering, Lai, Jih-Sheng, Meehan, Kathleen, Scales, Wayne A. |
| Publisher | Virginia Tech |
| Source Sets | Virginia Tech Theses and Dissertation |
| Detected Language | English |
| Type | Thesis |
| Format | application/pdf |
| Rights | In Copyright, http://rightsstatements.org/vocab/InC/1.0/ |
| Relation | Kim_AD_T_2011.pdf |
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