<p>To identify design errors that escape pre-silicon verification, post-silicon validation is becoming an important step in the implementation fl.ow of digital integrated circuits. While many debug problems are tackled on testers, there are hard-to-find design errors that are activated only in-system. A key challenge during in-system debugging is to acquire data from internal circuit's nodes in real-time. In this thesis, we propose several techniques to address this problem, ranging from resource-efficient and programmable trigger units to automated selection of trace signals to a distributed architecture for embedded logic analysis.</p><p>Deciding when to acquire data on-chip is done using trigger units. Because there is an inherent tradeoff between the size of the trigger units and the types of events that can be programmed into them, we first explore a resource-efficient and programmable trigger unit implementation. We show how the on-chip buffers used for data acquisition can be leveraged to store information regarding the logic functions that are programmed at runtime as the trigger events. This reduces the requirement in terms of logic resources for the trigger unit, while enlarging the set of programmable trigger events supported by these resources. We also propose a new algorithm to automatically map trigger events onto the proposed trigger unit.</p><p>Next we shift the focus from the trigger units to the sample units available onchip. Once the real-time debug experiment has been completed, the amount of data available to the user is limited by the capacity of the on-chip trace buffers. For logic bugs, where the circuit implementation matches the physical prototype, we show how the structural information from the circuit netlist can be leveraged to expand the amount of data made available off-line to the user. To ensure that data expansion can scale as the amount of debug data that is acquired increases, we propose a fast algorithm that leverages the bitwise parallelism of logic operations available in the instruction set of microprocessors. In a follow-up chapter, we also discuss how trace signals can be automatically selected in order to improve the amount of data that can be restored off-line. To achieve this objective, we propose two new metrics and two new algorithms for automatically identifying the circuit nodes which, if traced, will aid data expansion for the neighboring nodes in the circuit.</p><p>The last contribution of this thesis is concerned with managing multiple trace buffers in complex designs with many logic blocks. We propose a new distributed embedded logic analysis architecture that can dynamically allocate the trace buffers at runtime based on the needs for debug data acquisition coming from multiple logic blocks. We also leverage the real-time offload capability through high-speed trace ports in order to extend the duration of a debug experiment. It is shown how with little investment in on-chip debug logic resources, the length of debug experiments can be expanded for multi-core designs without increasing the number of on-chip trace buffers.</p> / Thesis / Doctor of Philosophy (PhD)
| Identifer | oai:union.ndltd.org:mcmaster.ca/oai:macsphere.mcmaster.ca:11375/17342 |
| Date | 04 1900 |
| Creators | Ko, Ho Fai |
| Contributors | Nicolici, Nicola, Electrical and Computer Engineering |
| Source Sets | McMaster University |
| Language | English |
| Detected Language | English |
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