The hierarchical abstract simulator is a multicomponent, multilevel discrete event model where each processor communicates with other processors by message passing. A methodology was developed to map the hierarchical abstract simulator onto distributed simulator architectures. The Intel's Personal Super Computer (iPSC) family with a concurrent-processing architecture is well suited for such simulation implementation. This thesis presents an alternative mapping realization of the hierarchical abstract simulator by using Intel's FORTRAN 286, FORTRAN 77 with extensions, on the iPSC computer (Hypercube). Algorithms for the hierarchical abstract simulator are provided in high level pseudo codes. A summary of iPSC system overview and programming concepts is described. Also, two examples are given for the illustration of our hypercube implementation. Finally, some experimental runs were made on the implementation, and comparisons of the performance (execution time) between sequential and parallel processor assignment are made.
| Identifer | oai:union.ndltd.org:arizona.edu/oai:arizona.openrepository.com:10150/276519 |
| Date | January 1987 |
| Creators | Wang, Yung-Hsin, 1957- |
| Publisher | The University of Arizona. |
| Source Sets | University of Arizona |
| Language | en_US |
| Detected Language | English |
| Type | text, Thesis-Reproduction (electronic) |
| Rights | Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author. |
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