This paper discusses an architectural anomaly observed on server processors of the AMD Zen microarchitecture: At a specific operating point, increasing the number of active cores reduces system power consumption while increasing performance more than proportionally to the additional cores. The occurrence of the anomaly is rooted in the hardware control loop for energy management and software-independent. Experiments show a connection to the AMD turbo frequency feature Max Core Boost Frequency (MCBF). In less efficient configurations, this feature could be employed from a processor’s perspective, even though it is not necessarily used on any core. Voltage measurements indicate that the availability of MCBF leads to a higher voltage from mainboard voltage regulators, subsequently raising power consumption unnecessarily. We describe the impact of this anomaly on the performance and energy-efficiency of several micro-benchmarks. The reduced power consumption when additional cores are enabled can lead to higher core frequencies and increased per-core-performance. The presented findings can be used to avoid inefficient core configurations and reduce the overall energy-to-solution.
| Identifer | oai:union.ndltd.org:DRESDEN/oai:qucosa:de:qucosa:74538 |
| Date | 23 April 2021 |
| Creators | von Elm, Christian, Ilsche, Thomas, Schöne, Robert, Bielert, Mario, Schmidl, Markus |
| Publisher | Association for Computing Machinery |
| Source Sets | Hochschulschriftenserver (HSSS) der SLUB Dresden |
| Language | German |
| Detected Language | English |
| Type | info:eu-repo/semantics/acceptedVersion, doc-type:conferenceObject, info:eu-repo/semantics/conferenceObject, doc-type:Text |
| Rights | info:eu-repo/semantics/openAccess |
| Relation | 978-1-4503-8331-8, 10.1145/3447545.3451193, info:eu-repo/grantAgreement/Deutsche Forschungsgemeinschaft/Sonderforschungsbereiche/164481002//Highly Adaptive Energy-Efficient Computing/HAEC |
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