Memory is an important part of any digital processing system. On-chip SRAM can be found in various levels of the memory hierarchy in a processor and occupies a considerable area of the chip. Leakage is one of the challenges which shrinking of technology has introduced and the leakage of SRAM constitutes a substantial part of the total leakage power of the chip due to its large area and the fact that many of the cells are idle without any access. In this thesis, we introduce asymmetric SRAM cells using stacked transistors which reduce the leakage up to 26% while increasing the delay of the cell by only 1.2% while reducing the read noise margin of the cell by only 15.7%. We also investigate an asymmetric cell configuration in which increases the delay by 33% while reduces the leakage up to 30% and reducing the read noise margin by only 1.2% compared to a regular SRAM cell.
| Identifer | oai:union.ndltd.org:unt.edu/info:ark/67531/metadc500021 |
| Date | 05 1900 |
| Creators | Ahrabi, Nina |
| Contributors | Kim, Hyoung Soo, 1977-, Zhang, Huliang, Wan, Yan |
| Publisher | University of North Texas |
| Source Sets | University of North Texas |
| Language | English |
| Detected Language | English |
| Type | Thesis or Dissertation |
| Format | Text |
| Rights | Public, Ahrabi, Nina, Copyright, Copyright is held by the author, unless otherwise noted. All rights Reserved. |
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