The trend to integrate more and more processing cores and memory cores into a single module has increased the overall size of chips to the point where global interconnects between sub-units are becoming harder and harder to route and meet timing rules and requirements. The traditional way of routing interconnects and the use of uniform, unidirectional, point to point busses may no longer be optimal for certain designs where metal layers and chip area for interconnects are limited. The need for a more flexible routing methodology is necessary and can be achieved by using routing and calibration techniques currently being implemented at board level design. This report proposes the use of non-uniform, bidirectional, and possibly multi-point loads global interconnects within a single chip module through the use of on chip calibration techniques to compensate for less restrictive wiring rules for certain chip designs. This report will also apply a widely used digital calibration technique to simulate the implementation on a field programmable gate array. / text
| Identifer | oai:union.ndltd.org:UTEXAS/oai:repositories.lib.utexas.edu:2152/28537 |
| Date | 17 February 2015 |
| Creators | Saetow, Anuwat |
| Source Sets | University of Texas |
| Language | English |
| Detected Language | English |
| Type | Thesis |
| Format | application/pdf |
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