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Design of A Systolic Array-Based FPGA Parallel Architecture for the BLAST Algorithm and Its Implementation

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1. http://rave.ohiolink.edu/etdc/view?acc_num=toledo1338478834

Identifer	oai:union.ndltd.org:OhioLink/oai:etd.ohiolink.edu:toledo1338478834
Date	13 December 2012
Creators	Guo, Xinyu
Publisher	University of Toledo / OhioLINK
Source Sets	Ohiolink ETDs
Language	English
Detected Language	English
Type	text
Source	http://rave.ohiolink.edu/etdc/view?acc_num=toledo1338478834
Rights	unrestricted, This thesis or dissertation is protected by copyright: all rights reserved. It may not be copied or redistributed beyond the terms of applicable copyright laws.