A Rayleigh/Rician fading channel based on Jakes¡¦ model is implemented by FPGA hardware in this thesis. Parameters, including vehicular speed, carrier frequency, quantization bits and internal clock rate, are carefully chosen according to the fading statistics. Verification of this fading channel hardware is carried out on Altera FPGA board with functional and time sequential test. Finally, performance of a differential PSK modem via fading and noisy channel is simulated and emulated in both software and hardware methods.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0828103-163403 |
| Date | 28 August 2003 |
| Creators | Wu, Yang-Ying |
| Contributors | Ken-Huang Lin, Ching-Piao Hung, Ju-Ya Chen, Jieh-Chian Wu |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0828103-163403 |
| Rights | restricted, Copyright information available at source archive |
Page generated in 0.0015 seconds