Return to search

Fault simulation and test pattern generation for synchronous and asynchronous sequential circuits /

Thesis (Ph. D.)--Virginia Polytechnic Institute and State University, 1993. / Vita. Abstract. Includes bibliographical references (leaves 1778-181). Also available via the Internet.

Identiferoai:union.ndltd.org:OCLC/oai:xtcat.oclc.org:OCLCNo/30805385
Date January 1993
CreatorsLee, Hyung Ki,
Source SetsOCLC
LanguageEnglish
Detected LanguageEnglish
SourceThis resource online

Page generated in 0.0018 seconds