It is widely recognized that device and interconnect fabrics at the nanoscale
will be characterized by a higher density of permanent defects and increased susceptibility
to transient faults. This appears to be intrinsic to nanoscale regimes
and fundamentally limits the eventual benefits of the increased device density, i.e.,
the overheads associated with achieving fault-tolerance may counter the benefits
of increased device density -- density-reliability tradeoff. At the same time, as devices
scale down one can expect a higher proportion of area to be associated with
interconnection, i.e., area is wire dominated. In this work we theoretically explore
density-reliability tradeoffs in wire dominated integrated systems. We derive an area
scaling model based on simple assumptions capturing the salient features of hierarchical
design for high performance systems, along with first order assumptions on
reliability, wire area, and wire length across hierarchical levels. We then evaluate
overheads associated with using basic fault-tolerance techniques at different levels
of the design hierarchy. This, albeit simplified model, allows us to tackle several
interesting theoretical questions: (1) When does it make sense to use smaller less
reliable devices? (2) At what scale of the design hierarchy should fault tolerance be applied in high performance integrated systems? In the second part of this thesis we explore perturbation-based computational
models as a promising choice for implementing next generation ubiquitous
information technology on unreliable nanotechnologies. We show the inherent robustness
of such computational models to high defect densities and performance
uncertainty which, when combined with low manufacturing precision requirements,
makes them particularly suitable for emerging nanoelectronics. We propose a hybrid
eNano-CMOS perturbation-based computing platform relying on a new style
of configurability that exploits the computational model's unique form of unstructured
redundancy. We consider the practicality and scalability of perturbation-based
computational models by developing and assessing initial foundations for engineering
such systems. Specifically, new design and decomposition principles exploiting
task specific contextual and temporal scales are proposed and shown to substantially
reduce complexity for several benchmark tasks. Our results provide strong evidence
for the relevance and potential of this class of computational models when targeted
at emerging unreliable nanoelectronics. / text
| Identifer | oai:union.ndltd.org:UTEXAS/oai:repositories.lib.utexas.edu:2152/7535 |
| Date | 01 June 2010 |
| Creators | Zykov, Andrey V. |
| Source Sets | University of Texas |
| Language | English |
| Detected Language | English |
| Format | electronic |
| Rights | Copyright is held by the author. Presentation of this material on the Libraries' web site by University Libraries, The University of Texas at Austin was made possible under a limited license grant from the author who has retained all copyrights in the works. |
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