We give an architecture of a storage system consisting of a storage medium made of unreliable memory elements and an error correction circuit made of a combination of noisy and noiseless logic gates that is capable of retaining the stored information with the lower probability of error than a storage system with a correction circuit made completely of noiseless logic gates. Our correction circuit is based on the iterative decoding of low-density parity check codes, and uses the positive effect of errors in logic gates to correct errors in memory elements. In the spirit of Marcus Tullius Cicero's Clavus clavo eicitur (one nail drives out another), the proposed storage system operates on the principle: error errore eicitur-one error drives out another. The randomness that is present in the logic gates makes these classes of decoders superior to their noiseless counterparts. Moreover, random perturbations do not require any additional computational resources as they are inherent to unreliable hardware itself. To utilize the benefits of logic gate failures, our correction circuit relies on two key novelties: a mixture of reliable and unreliable gates and decoder rewinding. We present a method based on absorbing Markov chains for the probability of error analysis, and explain how the randomness in the variable and check node update function helps a decoder to escape to local minima associated with trapping sets.
| Identifer | oai:union.ndltd.org:arizona.edu/oai:arizona.openrepository.com:10150/621739 |
| Date | 09 1900 |
| Creators | Ivanis, Predrag, Vasic, Bane |
| Contributors | Univ Arizona, Dept Elect & Comp Engn |
| Publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC |
| Source Sets | University of Arizona |
| Language | English |
| Detected Language | English |
| Type | Article |
| Rights | © 2016 IEEE |
| Relation | http://ieeexplore.ieee.org/document/7509624/ |
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