Tri-state structures are used to implement multiplexers and buses because these
structures are faster than AND/OR logic structures. But testing of tri-state structures has
some issues associated with it. A stuck open control line of a tri-state gate will cause
some lines in the circuit to float and take unknown values. A stuck-on control line can
cause fighting when the two drivers connected to the same node drive different values.
This thesis develops new gate level fault models and dynamic test patterns that take care
of these problems. The models can be used with traditional stuck-at and transition fault
automatic test pattern generation (ATPG) to ensure high fault coverage.
This research focuses on producing good test coverage with reduced effort for tristate
and pass transistor structures. We do circuit level modeling to help develop and
validate gate level models, which can be used in production ATPG. We study the two
primary effects of interest, capacitive coupling and leakage, and analyze the tri-state
structures using these two effects. Coupling and leakage can cause a Z or X state to be
seen as 0 or 1 in some cases. We develop parameterized models of behavior of common
structures using these effects and some parameters such as number of fan-ins. We also
develop gate level models of tri-state circuits that would replace the tri-state library cells in the ATPG engine. This work develops a methodology to make tri-state and pass
transistor circuit structures more usable in the industry.
| Identifer | oai:union.ndltd.org:tamu.edu/oai:repository.tamu.edu:1969.1/2730 |
| Date | 01 November 2005 |
| Creators | Parikh, Shaishav Shailesh |
| Contributors | Hu, Jiang, Walker, Duncan M. |
| Publisher | Texas A&M University |
| Source Sets | Texas A and M University |
| Language | en_US |
| Detected Language | English |
| Type | Book, Thesis, Electronic Thesis, text |
| Format | 156409 bytes, electronic, application/pdf, born digital |
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