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Economic lot scheduling for multiple products on parallel processors

No description available.
Identiferoai:union.ndltd.org:GATECH/oai:smartech.gatech.edu:1853/25481
Date08 1900
CreatorsCarreno, Jose Juan
PublisherGeorgia Institute of Technology
Source SetsGeorgia Tech Electronic Thesis and Dissertation Archive
Detected LanguageEnglish
TypeDissertation
RightsAccess restricted to authorized Georgia Tech users only.

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