Threshold logic gates allow for complex multi-input functions to be implemented using a single gate reducing the power and area of the circuit. Clocked based threshold gates have the additional advantage of its capability of being nanopipelined to increase network throughput. To produce a threshold network the proposed algorithm accepts a traditional algebraic boolean network as an input and resynthesizes it into a nanopipelined threshold logic network. The algorithm is the first to our knowledge that synthesizes in a manner to not only minimize the number of clusters produced from synthesizing the algebraic boolean network but also to minimize associated buffer insertion overhead in producing a clocked threshold gate network.
Identifer | oai:union.ndltd.org:siu.edu/oai:opensiuc.lib.siu.edu:theses-1701 |
Date | 01 August 2011 |
Creators | Pierce, Luke |
Publisher | OpenSIUC |
Source Sets | Southern Illinois University Carbondale |
Detected Language | English |
Type | text |
Format | application/pdf |
Source | Theses |
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