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Model stárnutí unipolárního tranzistoru / FET aging model

This work deals with problems aging of unipolar transistors. In theoretical parts are described the mechanisms which causing aging unipolar transistors and way leading to the restriction the change of parameters in time. The measurement and data evaluation was built on theoretical knowledge. The model of aging FET is a result of this works; it is creating extraction of data from measured data. Finally, the degradation constants are evaluation from this data. This FET aging model is easy to use in simulators of electronics circuits including aging simulations (e.g. ELDO).

Identiferoai:union.ndltd.org:nusl.cz/oai:invenio.nusl.cz:217242
Date January 2008
CreatorsNovosád, Jiří
ContributorsLegát, Pavel, Semiconductor, Aleš Litschmann, ON
PublisherVysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií
Source SetsCzech ETDs
LanguageCzech
Detected LanguageEnglish
Typeinfo:eu-repo/semantics/masterThesis
Rightsinfo:eu-repo/semantics/restrictedAccess

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