Division is one of the most fundamental arithmetic operations and is used extensively in engineering, scientific, mathematical and cryptographic applications. The implementation of arithmetic operation such as division, is complex and expensive in hardware. Unlike addition and subtraction, division requires several iterative computational steps on given operands to produce the result. Division, in the past has often been perceived as an infrequently used operation and received not as much attention but it is one of the most difficult operations in computer arithmetic. The techniques of implementation in hardware of such an iterative computation impacts the speed, the area and power of the digital circuit. For this reason, we consider two division algorithms based on their step size in shift. Algorithm 1 operates on fixed shift step size and has a fixed number of iteration while the Algorithms 2 operates on variable shift step size and requires considerably fewer number of iterations. In this thesis, technique is provided to save power and speed up the overall computation. It also looks at different design goal strategies and presents a comparative study to asses how each of the two design perform in terms of area, delay and power consumption. / Graduate / salmankh@uvic.ca
| Identifer | oai:union.ndltd.org:uvic.ca/oai:dspace.library.uvic.ca:1828/6394 |
| Date | 29 July 2015 |
| Creators | Khan, Salman |
| Contributors | Gebali, Fayez, Ibrahim, Atef |
| Source Sets | University of Victoria |
| Language | English, English |
| Detected Language | English |
| Type | Thesis |
| Rights | Available to the World Wide Web, http://creativecommons.org/publicdomain/zero/1.0/ |
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