A stacked microchannel heat sink was developed to provide efficient cooling for microelectronics devices at a relatively low pressure drop while maintaining chip temperature uniformity. Microfabrication techniques were employed to fabricate the stacked microchannel structure, and experiments were conducted to study its thermal performance. A total thermal resistance of less than 0.1 K/W was demonstrated for both counter flow and parallel flow configurations. The effects of flow direction and interlayer flow rate ratio were investigated. It was found that for the low flow rate range the parallel flow arrangement results in a better overall thermal performance than the counter flow arrangement; whereas, for the large flow rate range, the total thermal resistances for both the counter flow and parallel flow configurations are indistinguishable. On the other hand, the counter flow arrangement provides better temperature uniformity for the entire flow rate range tested. The effects of localized heating on the overall thermal performance were examined by selectively applying electrical power to the heaters. Numerical simulations were conducted to study the conjugate heat transfer inside the stacked microchannels. Negative heat flux conditions were found near the outlets of the microchannels for the counter flow arrangement. This is particularly evident for small flow rates. The numerical results clearly explain why the total thermal resistance for counter flow arrangement is larger than that for the parallel flow at low flow rates.
In addition, laminar flow inside the microchannels were characterized using Micro-PIV techniques. Microchannels of different width were fabricated in silicon, the smallest channel measuring 34 mm in width. Measurements were conducted at various channel depths. Measured velocity profiles at these depths were found to be in reasonable agreement with laminar flow theory. Micro-PIV measurement found that the maximum velocity is shifted significantly towards the top of the microchannels due to the sidewall slope, a common issue faced with DRIE etching. Numerical simulations were conducted to investigate the effects of the sidewall slope on the flow and heat transfer. The results show that the effects of large sidewall slope on heat transfer are significant; whereas, the effects on pressure drop are not as pronounced.
| Identifer | oai:union.ndltd.org:GATECH/oai:smartech.gatech.edu:1853/4873 |
| Date | 30 November 2004 |
| Creators | Wei, Xiaojin |
| Publisher | Georgia Institute of Technology |
| Source Sets | Georgia Tech Electronic Thesis and Dissertation Archive |
| Language | en_US |
| Detected Language | English |
| Type | Dissertation |
| Format | 2314346 bytes, application/pdf |
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