To days , computer systems are applied in safety critical areas such as military, aviation, intensive health care, industrial control, space exploration etc. All these areas demand highest possible reliability of functional operation. However, ionized particles and radiation impact on current semiconductor hardware leads inevitable to faults in the system. It is expected that such phenomena will be observed much more often in the future due to the ongoing miniaturisation of hardware structures. In this thesis we want to tackle the question of how system software should be designed in the event of such faults, and which fault tolerance features it should provide for highest reliability. We also show how the system software interacts with the hardware to tolerate these faults. In a first step, we analyse and further develop the theory of fault tolerance to understand the different ways how to increase the reliability of a system. Ultimately, the key is to use redundancy in all its different appearances. We we revise and further develop the general algorithm of fault tolerance (GAFT) with its three main processes hardware testing, preparation for recovery and the recovery procedure as our approach to the design of a fault tolerant system. For each of the three processes, we analyse the requirements and properties theoretically and give possible implementation scenarios. Based on the theoretical results, we derive an Oberon based programming language with direct support of the three processes of GAFT. In the last part of the thesis, we analyse a simulator based proof of concept implementation of a novel fault tolerant processor architecture (ERRIC) and its newly developed runtime system feature wise and performance wise.
| Identifer | oai:union.ndltd.org:bl.uk/oai:ethos.bl.uk:567824 |
| Date | January 2012 |
| Creators | Kägi, Thomas |
| Publisher | London Metropolitan University |
| Source Sets | Ethos UK |
| Detected Language | English |
| Type | Electronic Thesis or Dissertation |
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