The distributions of synchronized clock signals to all elements of a computing system is very important. Fletcher's clock patent is a good solution to this problem. The difficulty with implementation is the tremendous number of interconnections among different clock elements. Two methods are proposed to reduce the number of interconnectons without loss of synchronization and fault-tolerant capability. An mth order clock is a circuit consisting of (3f+1) ** (2** (m-1)) (m-1)th order clocks. Fletcher's clock patent is a 0th order clock. Starting with 0th order clocks, an mth order clock circuit can be built systematically. An mth order clock circuit can generate (3f+1)**(2**m) synchronized clock signals with (m + 1) (3f+ 1) ** ( 2**m) interconnections instead of (3f+1) ** (2*2**m) • Its fault-tolerant capability is also considered. Another type of connection is called Iterative Type, which is further classified into Cascaded Type, Scattering Type and 2-dimensional Type. Each type has its own characteristics. / Master of Science
| Identifer | oai:union.ndltd.org:VTETD/oai:vtechworks.lib.vt.edu:10919/76003 |
| Date | January 1978 |
| Creators | Fan, Tzu-I Jonathan |
| Contributors | Electrical Engineering |
| Publisher | Virginia Polytechnic Institute and State University |
| Source Sets | Virginia Tech Theses and Dissertation |
| Language | English |
| Detected Language | English |
| Type | Thesis, Text |
| Format | iii, 68 leaves, application/pdf, application/pdf |
| Rights | In Copyright, http://rightsstatements.org/vocab/InC/1.0/ |
| Relation | OCLC# 39884787 |
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