With the growing demand of embedded graphics applications, how to provide an efficient graphics hardware acceleration solution has drawn much attention. It is well known that computer graphics contains two major domains: two-dimensional (2D) and three-dimensional (3D) graphics. Each domain owns large amounts of applications, such that general embedded platforms will require both graphics acceleration supports. This thesis proposes an advanced texture unit architecture which can provide various 3D texture filtering functions including trilinear, anistrophics filtering etc , and 2D coloring, painting, and texturing functions. Our proposed design consists of a core computation unit, and a set of data registers. The equations for those supported functions are decomposed into a series of basic arithmetic operations such as multiply-add-accumulation, multiply, etc executed by the core computation unit. To evaluate those equations for each pixel may require some pre-computed parameters which will be computed outside our unit in advance by the system¡¦s micro-controller. The equations can be computed by our texture unit based on the selected finite-state machine sequences which is stored in the on-chip control table. By updating those sequences can change the functionality provided by our chip. The overall cost of the proposed unit is about 28.36k gates. In addition to various texturing functions, this thesis also proposes an implementation of texture function for high-dynamic range (HDR) textures. HDR textures can provide various color details according to the frame¡¦s global illumination environment. Therefore, the 3D rendering system has to incorporate a tone-mapping mechanism to map the HDR image into normal color range of output display system. To reduce the overall tone-mapping implementation cost, this thesis uses an extra accumulator between the standard per-fragment rendering pipeline stages to accumulate the global illumination intensity based on the depth comparison result of the incoming pixel. After all of the pixels have passed through the pipeline stages, every pixel of the stored rendering result will be fetched into a mapping unit which will generate its mapping color in the normal dynamic range. The overall cost of the additional
hardware for the realization of HDR textures is about 6.98k gates.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0905111-140430 |
| Date | 05 September 2011 |
| Creators | Li, Kuen-Wei |
| Contributors | Yun-Nan Chang, Shian-Rung Kuang, Shen-Fu Hsiao |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0905111-140430 |
| Rights | unrestricted, Copyright information available at source archive |
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