Electromigration continues to be one of the important failure mechanisms limiting the attainment of higher levels of reliability in sub-micron geometry VLSI circuits. Successful management of electromigration in future requires adoption of effective statistical process control techniques, in addition to the traditional quality control tests and inspections. The aim of this project was to develop a test structure and test methodology to monitor electromigration for metallisation process control. Based on analysis and some preliminary measurements on chequerboards, a new test structure and methodology was proposed to monitor electromigration. 'Chequerboards' are dense patterns of clear and opaque squares of metal film over silicon. As part of this study, an electromigration test chip was designed. It consists of two designs: The design EU9101 mainly contains chequerboards while EU9102 contains conventional and other electromigration test structures for comparative assessment. The chip design, fabrication and measurement details including the instrumentation aspects are also given in the thesis. One of the key process parameters, namely, linewidth is chosen to demonstrate the sensitivity of the proposed methodology to monitor electromigration. Possible applications of the new structure in electromigration measurements, other than process monitoring are also discussed. The thesis also contains a review of the electromigration measurement techniques, some measurements using the conventional test structure and a detailed discussion on the limits of conventional tests.
| Identifer | oai:union.ndltd.org:bl.uk/oai:ethos.bl.uk:660956 |
| Date | January 1992 |
| Creators | Ravindra, M. |
| Publisher | University of Edinburgh |
| Source Sets | Ethos UK |
| Detected Language | English |
| Type | Electronic Thesis or Dissertation |
| Source | http://hdl.handle.net/1842/14260 |
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