This thesis reports on a study into the fabrication of metal oxide silicon field effect transistors using electron beam lithography to pattern features with dimensions down to 100nm and below. The study is in an area of extensive research, with devices at these dimensions of interest for future generations of integrated circuit manufacture. The design and construction of a high resolution electron beam system is reported. The system is based on a very high resolution scanning electron microscope equipped with a thermal field emission gun. Chemically amplified resist processes, for electron beam lithography, have been characterised for silicon device fabrication and sub 100nm patterns have been demonstrated. The development of a fabrication process for silicon devices, with dimensions down to 100nm, is described. The process uses electron beam lithography for all levels of patterning and electrical measurements are reported for a range of the fabricated devices. Devices fabricated in this study are used to explore a novel width modification technique using focused ion beam milling to reduce the current drive of individual transistors. The transistors are characterised before and after modification and electrical measurements are presented which provide the basis for a new chip modification strategy.
| Identifer | oai:union.ndltd.org:bl.uk/oai:ethos.bl.uk:663028 |
| Date | January 1999 |
| Creators | Travis, David William |
| Publisher | University of Edinburgh |
| Source Sets | Ethos UK |
| Detected Language | English |
| Type | Electronic Thesis or Dissertation |
| Source | http://hdl.handle.net/1842/14571 |
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