The Discrete Cosine Transform(DCT) is the basis for current video standards like H.261, JPEG and MPEG. Since the DCT involves matrix multiplication, it is a very computationally intensive operation. Matrix multiplication entails repetitive sum of products which are carried out numerous times during the DCT computation. Therefore, as a result of the multiplications, a significant amount of switching activity takes place during the DCT process. This thesis proposes a number of new implementation schemes that reduce the switching capacitance within a DCT processor for either JPEG or MPEG environment. A number of generic schemes for low power VLSI implementation of the DCT are presented in this thesis. The schemes target reducing the effective switched capacitance within the datapath section of a DCT processor. Switched capacitance is reduced through manipulation and exploitation of correlation in pixel and cosine coefficients during the computation of the DCT coefficients. The first scheme concurrently processes blocks of cosine coefficient and pixel values during the multiplication procedure, with the aim of reducing the total switched capacitance within the multiplier circuit. The coefficients are presented to the multiplier inputs as a sequence, ordered according to bit correlation between successive cosine coefficients. The ordering of the cosine coefficients is applied to the columns. Hence the scheme is referred to as <i>column-based</i> processing. Column-Based processing exhibits power reductions of up to 50% within the multiplier unit. Another scheme, termed <i>order-based</i>, is based on the ordering of the cosine coefficients based on row segments. The scheme also utilises bit correlation between successive cosine coefficients. The effectiveness of this scheme is reflected in a power savings of up to 245. The final scheme is based on manipulating data representation of the cosine coefficients, through cosine word coding, in order to facilitate for a shift-only computational process. This eliminates the need for the multiplier unit, which poses a significant overhead in terms of power consumption, in the processing element. A maximum power saving of 41% was achieved with this implementation.
| Identifer | oai:union.ndltd.org:bl.uk/oai:ethos.bl.uk:657415 |
| Date | January 2001 |
| Creators | Masupe, Shedden |
| Publisher | University of Edinburgh |
| Source Sets | Ethos UK |
| Detected Language | English |
| Type | Electronic Thesis or Dissertation |
| Source | http://hdl.handle.net/1842/12604 |
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