The Electrically Erasable Programmable ROM (EEPROM) is used in applications such as microcontrollers and mass storage media. Each of these markets is rapidly expanding. However, EEPROMs are particularly susceptible to reliability problems, since they must survive severe voltage and current stressing. This has a knock on effect, since operating speed must be reduced, to increase reliability. Motorola's implementation of the EEPROM is the Floating Gate Electron Tunnelling MOS (FETMOS), which has been adopted for study in this thesis. An analytic model has been developed for the FETMOS, which encompasses transient response, threshold window and reliability. A good correlation has been shown between modelled data and experimental results, testifying to the model's accuracy. The effect of basic design parameters upon threshold window has been characterised, thus indicating how processing variations may be used to tailor the EEPROM threshold window. Equally, the model may be used to predict the effect of sizing down a circuit - this is important as integration densities escalate. Program endurance is the most pressing reliability issue. Modelling has indicated that large improvements may be made in this by increasing the floating gate/drain overlap, with little effect on threshold window. A novel experiment has then been devised to monitor the effect of floating gate/drain overlap and doping species, upon EEPROM reliability. For this, transistor arrays with a spectrum of well defined gate/drain offsets have been produced. The results of these are consistent with the model. It has also been found that the chemistry of the dopant has only a tangential effect upon reliability.
| Identifer | oai:union.ndltd.org:bl.uk/oai:ethos.bl.uk:642796 |
| Date | January 1993 |
| Creators | Chester, Anthony James |
| Publisher | University of Edinburgh |
| Source Sets | Ethos UK |
| Detected Language | English |
| Type | Electronic Thesis or Dissertation |
| Source | http://hdl.handle.net/1842/13369 |
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