Bit-Serial architecture and Gallium Arsenide have essentially been mutually exclusive fields in the past. Digital Gallium Arsenide integrated circuits have increasingly adopted the conventional approach of bit-parallel structures that do not always suit the properties and problems of the technology. This thesis proposes an alternative by using a least significant bit first bit-serial architecture, and presents a group of 'cells' designed for signal processing applications. The main features of the cells include the extensive use of pseudo-dynamic latches for pipelining, modularity, and programmability. The logic circuits are mainly based on direct-coupled FET logic. They are also compatible with silicon ECL circuits. The target clock rates for these cells are 500MHz, at least ten times faster than previous silicon bit-serial circuits. The differences between GaAs and silicon technologies meant that the cells were designed from circuit level upwards. Further to these cells, a multi-level signaling scheme has been developed to substantially alleviate off-chip signaling. Synchonisation between signals are simplified, improving even further on the conventional bit-serial system, especially at the high bit-rates encountered in GaAs circuits. For on-chip signals, a single phase clock scheme has been developed for the GaAs cells, which maintains the low clock loading and high speed charactersitics of the pseudo-dynamic cells, while substantially simplifying clock distribution and generation. Two novel latch designs are proposed for this scheme. Test results available have already proved the concepts behind the two-phase clocking scheme, the latches, and the multi-level scheme. Further tests are taking place to establish their speed performance.
| Identifer | oai:union.ndltd.org:bl.uk/oai:ethos.bl.uk:653631 |
| Date | January 1990 |
| Creators | Lam, S. C. K. |
| Publisher | University of Edinburgh |
| Source Sets | Ethos UK |
| Detected Language | English |
| Type | Electronic Thesis or Dissertation |
| Source | http://hdl.handle.net/1842/11027 |
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