Electromagnetic interference has become an important topic of research as more and more radios are getting integrated around us. One of the well-known techniques to lower the EMI from integrated circuits is to use spread spectrum techniques [1]. Traditionally, phase locked loops (PLL) have been utilized to generate SSC clocks. The PLL’s consist of a high power voltage controlled oscillator. This is undesirable in scenarios wherein the low power operation is required such as medical implants. In addition, the PLL loop band width impacts the intentional jitter. The current work introduces a non-PLL (Phase Locked Loops) modulator to enable low power operation. A chaotic modulation profile has been proposed to efficiently spread the frequency spectrum. Since there is no feedback loop, the input deterministic jitter is passed to the output. One of the proposed applications is biomedical telemetry. With the advent of more and more implantable and non-implantable devices for monitoring various physiological paramete s, the operating frequency band will become more and more clouded. Hence, there is a need to lower the EM signature of the transmitter. In addition, the transmitters need to be able to shift the operating frequency as per the MAC protocols [2] [3] to be able to operate in a channel with least interference. Also, the transmitter needs to be low power to conserve power. The interference path from the transmitter lies within the body and outside the body. The in body path to the adjacent transmitter depends upon the operating frequency and the distance from source [4]. The proposed architecture is able to integrate within DOSS (dynamic open spectrum sharing) protocol and is able to adjust the frequency of operation based on the communication from the MAC controller [5]. A system level model has been built to simulate an implanted transmitter and tested with a 10s sleep signal obtained through Physionet [6]. Another proposed application is generation of on die clocks. The ever increasing speed of clocks and higher data rates leads to increased radiated coupling. Traditionally PLL’s have been utilized for generating the dithered clock on die [7]. Multi clock domains from the same PLL clock source [8] require different amount of spreading. The proposed frequency modulator could be used in such scenarios to allow the clock domains to be independently controlled from the source PLL. The frequency modulator and a chaotic generator have been fabricated on AMS 6 metal layer 0.18µm technology. The frequency modulator was fabricated, characterized and measurements have been presented. The current work achieves a low power through circuit techniues by proposing a non-PLL based topology thus excluding the use of high power consuming VCO. Low emission is achieved using a variety of modulation profiles (periodic and chaotic) for spreading the bandwidth of the modulated spectrum. The current work was supported by European Research Council and Intel Research Labs through various grants.
| Identifer | oai:union.ndltd.org:bl.uk/oai:ethos.bl.uk:726905 |
| Date | January 2015 |
| Creators | Saraswat, Ruchir |
| Contributors | Rodriguez-Villegas, Esther |
| Publisher | Imperial College London |
| Source Sets | Ethos UK |
| Detected Language | English |
| Type | Electronic Thesis or Dissertation |
| Source | http://hdl.handle.net/10044/1/53381 |
Page generated in 0.0086 seconds