Exploiting the advantageous properties of Ferroelectric Liquid Crystals (FLCs) in Liquid-Crystal-on-Silicon (LCoS) microdisplay devices has proved very challenging for several reasons. Means of controlling the small cell gap required for optimum electro-optical performance (typically around 0.8 µm) even across the small active area of such displays had to be developed. Improving the compatibility of the silicon chip with this particular liquid crystal configuration and its intrinsically high susceptibility to cosmetic defects was also required. This thesis presents some process development work aimed at solving these issues. An advanced post-processing procedure for the preparation of silicon backplanes relying on the use of chemical mechanical polishing (CMP) has been employed to prepare realistic sample surfaces for studying the resulting topography on the liquid crystal layer. A process sequence for producing integrated peripheral spacer structures on silicon backplanes is presented and its compatibility with ferroelectric liquid crystals assessed. The use of thin films deposited on the back of silicon wafers for flattening the silicon chip in order to improve the cell gap uniformity across the device was demonstrated. It is also shown that patterning of this stress compensation layer offers the possibility of controlling the symmetry of its flattening effect. Such option is advantageous in terms of the additional latitude it provides in terms of IC design.
| Identifer | oai:union.ndltd.org:bl.uk/oai:ethos.bl.uk:657843 |
| Date | January 2006 |
| Creators | Miremont, Christophe |
| Publisher | University of Edinburgh |
| Source Sets | Ethos UK |
| Detected Language | English |
| Type | Electronic Thesis or Dissertation |
| Source | http://hdl.handle.net/1842/15401 |
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