The thesis is mainly in algorithm design and implementation of hardware circuit of baseband signal processing at the transceiver of 2450 MHz band chirp spread spectrum in IEEE 802.15.4a ¡V 2007 Low Rate-Wireless Personal Area Network (LR-WPAN). Due to the characteristic of LR-WPAN such as low cost, low power consumption, small size and easy to implementation, we have to take the complexity and the system performance into consideration.
In this thesis, we study on the algorithm design of baseband signal, and analysis the simulation result. At the transmitter, following the specification and realize it. At the receiver, designing the algorithm including the packet detection, energy detection and down-sampling, carrier frequency offset estimation and compensation, timing synchronization, and bi-orthogonal demapper. The system performance after quantizing is 3dB better than the receiver sensitivity we expected. After finishing the algorithm design of the transceiver, we implement the baseband signal circuit by using Verilog Code. Finally, we make an application to National Chip Implementation Center (CIC), and will measure the circuit after the chip tape out. The circuit is fabricated in a 0.18-£gm CMOS technology.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0823111-175621 |
| Date | 23 August 2011 |
| Creators | Lin, Shune-dao |
| Contributors | Jyh-Horng Wen, Chin-Liang Wang, Yu-Te Su, Chih-Peng Li, Char-Dir Chung |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0823111-175621 |
| Rights | user_define, Copyright information available at source archive |
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