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A 5 GHZ low power, low jitter and fast settling phase locked loop architecture for wireline and wireless transceiver

Thesis (Ph. D.)--Washington State University, August 2008. / Includes bibliographical references (p. 84-85).

Identiferoai:union.ndltd.org:OCLC/oai:xtcat.oclc.org:OCLCNo/252264962
Date January 2008
CreatorsUpadhyaya, Parag.
Source SetsOCLC
LanguageEnglish
Detected LanguageEnglish
SourceOnline access for everyone

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