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Design of a phase locked loop clock recovery and data re-timing circuit for 50 to 800 mbps NRZ-L data

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1. https://stars.library.ucf.edu/rtd/1828

Identifer	oai:union.ndltd.org:ucf.edu/oai:stars.library.ucf.edu:rtd-2827
Date	01 July 2000
Creators	Eisenhauer, Nancy L.
Publisher	STARS
Source Sets	University of Central Florida
Language	English
Detected Language	English
Type	text
Source	Retrospective Theses and Dissertations