The aim of this thesis is the acquisition of data from the AD converter and it’s transfer via the JESD204B interface to FPGA with the following transformation and transfer to PC through 100G Ethernet or PCI Express interface. The first part of the thesis is focused on the introduction to used technologies and hardware and analysis of the solution of this project. Second part of the thesis describes solution and it’s functionality. I created HDL design which allows to transfer data from AD converter using both of the interfaces mentioned above. I also created software application for OS Linux which allows to receive and store incoming data in PC. In the end, the results of the measurement using the converter board are presented and discussed.
| Identifer | oai:union.ndltd.org:nusl.cz/oai:invenio.nusl.cz:413262 |
| Date | January 2020 |
| Creators | Hadámek, Jakub |
| Contributors | Petyovský, Petr, Valach, Soběslav |
| Publisher | Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií |
| Source Sets | Czech ETDs |
| Language | Czech |
| Detected Language | English |
| Type | info:eu-repo/semantics/masterThesis |
| Rights | info:eu-repo/semantics/restrictedAccess |
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