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ITERATIVE RELAXATION ALGORITHM: AN EFFICIENT AND IMPROVED METHOD FOR CIRCUIT SIMULATION USED IN SIERRA: VHDL-AMS SIMULATOR

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Identiferoai:union.ndltd.org:OhioLink/oai:etd.ohiolink.edu:ucin1034358459
Date15 October 2002
CreatorsBALAKRISHNAN, GEETA
PublisherUniversity of Cincinnati / OhioLINK
Source SetsOhiolink ETDs
LanguageEnglish
Detected LanguageEnglish
Typetext
Sourcehttp://rave.ohiolink.edu/etdc/view?acc_num=ucin1034358459
Rightsunrestricted, This thesis or dissertation is protected by copyright: all rights reserved. It may not be copied or redistributed beyond the terms of applicable copyright laws.

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