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An 8 bit Serial Communication module Chip Design Using Synopsys tools and ASIC Design Flow Methodology

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Identiferoai:union.ndltd.org:OhioLink/oai:etd.ohiolink.edu:ysu152703879322399
Date23 May 2018
CreatorsMunugala, Anvesh
PublisherYoungstown State University / OhioLINK
Source SetsOhiolink ETDs
LanguageEnglish
Detected LanguageEnglish
Typetext
Sourcehttp://rave.ohiolink.edu/etdc/view?acc_num=ysu152703879322399
Rightsunrestricted, This thesis or dissertation is protected by copyright: all rights reserved. It may not be copied or redistributed beyond the terms of applicable copyright laws.

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