ATM is based on the efforts of the ITU-T Broadband Integrated Services Digital
Network (B-ISDN) standard. It was originally conceived as a high-speed transfer
technology for voice, video, and data over public networks. The ATM Forum has
broadened the ITU-T�s vision of ATM for extended use over public and private networks,
multi-protocol support and mobile ATM. There are also some ATM applications in High
Performance Computing (HPC).
ATM is a packet switching technique based on a virtual circuit mechanism. Data
flows are statistically multiplexed and communication resources are dynamically shared.
Therefore the high performance ATM switch is essential for quality of services (QoS).
This thesis introduces typical ATM switch architecture design and analyses
design problems. The research objective is to propose a switch architecture design that
can solve or improve those existing problems to achieve a superior performance. The
research goal is an integrated ATM switch architecture that will handle both unicast and
multicast packets. Unlike the usual design for the multicast ATM switch which
concentrates on a cell copy network with a unicast switching network, the proposed
switch architecture processes the network packets in a single switching block, and allows
unicast and multicast packets to co-exist without competing. The switch design has a
simple topology and operation principle and is easy to implement. Furthermore, no copy
network is required. Three major components are proposed to form the core of the new
switch architecture: the parallel buffering strategy for improved buffer performance, the
fast table lookup algorithm for packet duplication and routing, and the relay ring
controller for solving the contention problem associated with multiple packets destined
for the same output port.
A mathematical model is presented and its numerical results are analysed. In
addition, the simulation algorithms for the proposed switching design are presented and
compared against the switching design with input and output buffering strategies. The
simulation results are also compared and analysed against the numerical results.
A multicast traffic model is also presented. Its performance calculation for the
proposed switch is achieved through simulation. Performance analysis is compared
against the output buffering switch under the same multicast traffic model.
The performance analysis shows that the proposed switch architecture achieves
high throughput with low cell loss rate and low time delay. Its performance can be as
good as the output buffering strategy or better. Therefore the proposed switch design has
solved the problems associated with input and output buffering.
This thesis also analyses the complexity of the proposed switch architecture and
suggests a topology to build a large scale ATM switch. The suitability and feasibility for
production implementation are also addressed.
| Identifer | oai:union.ndltd.org:ADTP/216627 |
| Date | January 2006 |
| Creators | Chen, Hong Xu, n/a |
| Publisher | Swinburne University of Technology. |
| Source Sets | Australiasian Digital Theses Program |
| Language | English |
| Detected Language | English |
| Rights | http://www.swin.edu.au/), Copyright Hong Xu Chen |
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