Return to search

Vysokorychlostní akviziční systém / High speed acquisition system

This master's thesis is focused on the design of a highspeed aquizition system which is based on FPGA and a highspeed AD converter with modern JESD204B interface. Considering the requirements, such as high samplig rate, the current range of available devices is limited. Therefore the market overview of the modern IC and modules was made. The resulting design is based on available modules, so the rached sampling rate is up to 5 GSa/s with 12bits resolution. Data from measurement are send to PC via Ethernet which uses lwIp stack and TEMAC core on Microblaze proccessor.

Identiferoai:union.ndltd.org:nusl.cz/oai:invenio.nusl.cz:377119
Date January 2018
CreatorsSvoboda, Tomáš
ContributorsKováč, Michal, Kubíček, Michal
PublisherVysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií
Source SetsCzech ETDs
LanguageCzech
Detected LanguageEnglish
Typeinfo:eu-repo/semantics/masterThesis
Rightsinfo:eu-repo/semantics/restrictedAccess

Page generated in 0.0021 seconds