In order to improve the sensitivity of an optical receiver, the gain and the collection area of the photo-detectors within the receiver should be increased. Detectors with internal gain such as avalanche photodiodes (APD) are usually used to increase the sensitivity of the receiver. One problem with APDs is the sensitivity of their gain to their bias voltage, which makes them challenging to be fabricated in a standard CMOS process due to variations in their gain. However, when an APD is biased over its breakdown voltage, it is sensitive to a single photon, hence, referred to as a single photon avalanche diodes (SPAD). The SPADs are photon-counting detectors, which are less sensitive to their bias voltage, and can be integrated with rest of the electronic circuitry that form an optical receiver. An avalanche diode requires dedicated circuits to be operated in the SPAD mode. These circuits make the diode insensitive to an incident photon for a duration that is known as deadtime. Unfortunately, The collection area of the PD, APD, and SPADs are limited to their capacitance. Hence, a large photo-detector leads to a larger capacitance, which reduces the bandwidth of the receiver. In this thesis, a photon counting optical receiver based on an array of SPADs is proposed which increases the collection area with a low output capacitance. The avalanche diode and peripheral circuits which operate and readout-out the SPAD array are fabricated in the commercially available UMC 0.18 μm CMOS process. Initially, the avalanche diode is tested and characterised. A high performance circuit is then designed and tested which is able to achieve short deadtimes up to 4 ns. Once the photon counting operation of the SPAD is verified, a numerical model is developed to investigate the influence of several factors, including the deadtime, on the performance of the photon-counting detector in a communication link. Based on the simulation results, which show the advantages of an array over a single detector, a prototype detector array of 64 asynchronous SPADs is designed and tested. This array uses a high-speed readout mechanism which is inspired by the current steering digital-to-analogue converters. Bit error ratio tests (BERT) verify the photon counting capability of the proposed detector, and a bit error rate of 1E-3 has been achieved at data rate of 100 Mbps. In addition, the array of SPAD is compatible with a front-end of conventional optical receiver which uses a photodiode as a photo detector.
| Identifer | oai:union.ndltd.org:bl.uk/oai:ethos.bl.uk:618386 |
| Date | January 2013 |
| Creators | Chitnis, Danial |
| Contributors | Collins, Steve |
| Publisher | University of Oxford |
| Source Sets | Ethos UK |
| Detected Language | English |
| Type | Electronic Thesis or Dissertation |
| Source | http://ora.ox.ac.uk/objects/uuid:5fd582dd-8167-4fe4-88f8-871ba905ade1 |
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