In addition, we can further reduce the power consumption by reducing the number of interconnects. We propose to use a quaternary (4-level) logic output to replace the binary (2-level) logic output, which will reduce the number of interconnect by half. A 6-bit current mode analog-to-quaternary converter (AQC) test chip is designed with special current mode quaternary logic functions. / The power reduction techniques are carried out in both circuit and system levels. At the circuit level, a new sub-stage design using voltage comparator is proposed to reduce power consumption without any performance degradation. At the system level, we observe that the signal-to-noise ratio (SNR) of a current mode pipelined ADC is proportional to the input current level, and the SNR of a pipelined ADC is dominated by the first few stages. Thus, it is possible to reduce the power consumption without significantly degrading the SNR by gradually reducing the current level of each stage along the pipeline. A 12-bit CMOS current mode pipelined ADC test chip is designed with a 0.35mum CMOS digital process. The measured signal-to-noise and distortion ratio (SNDR), spurious free dynamic range (SFDR) and total harmonic distortion (THD) are 64.90dB, 67.79dB and -67.02dB, respectively. The effective number of bit (ENOB) achieved is 10.49-bit and the calculated FOM is 1.31pJ, which has the lowest power consumption among reported current mode ADCs. / The supply voltage of advanced CMOS technology is reduced to 1V or less. It is very difficult to design high performance analog circuit at this supply voltage because of the limited dynamic range. One possible solution is to use current mode circuit technique which is less sensitive to the limited dynamic range. Moreover, current mode circuit is more suitable for low voltage applications compare to the conventional voltage mode circuit. This research uses analog-to-digital converter (ADC) as a vehicle to investigate current mode design techniques with a main focus on power reduction. / Chan Chi Hong. / "September 2007." / Adviser: C. F. Chan. / Source: Dissertation Abstracts International, Volume: 69-08, Section: B, page: 4923. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2007. / Includes bibliographical references. / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstracts in English and Chinese. / School code: 1307.
| Identifer | oai:union.ndltd.org:cuhk.edu.hk/oai:cuhk-dr:cuhk_344127 |
| Date | January 2007 |
| Contributors | Chan, Chi Hong., Chinese University of Hong Kong Graduate School. Division of Electronic Engineering. |
| Source Sets | The Chinese University of Hong Kong |
| Language | English, Chinese |
| Detected Language | English |
| Type | Text, theses |
| Format | electronic resource, microform, microfiche, 1 online resource (xiv, 138 p. : ill.) |
| Rights | Use of this resource is governed by the terms and conditions of the Creative Commons “Attribution-NonCommercial-NoDerivatives 4.0 International” License (http://creativecommons.org/licenses/by-nc-nd/4.0/) |
Page generated in 0.0022 seconds