Continuous process scale-down and emerging markets for low-power/low-voltage mobile
systems call for low-voltage analog integrated circuits. Switched-capacitor circuits are the
building blocks for analog signal processing and will encounter severe overdrive problems when
operating at low-voltage conditions. There are several well-known techniques to bypass the
problem. These approaches include: (1) The clock boosting schemes (e.g. 2VDD clock signal)
which cannot be used in submicron low-voltage CMOS processes as gate oxide can only tolerate
the technology's maximum voltage (VDD). (2) The use of scaled/lower threshold transistors, which
are not always scalable to very low voltage supplies as it could suffer from an unacceptable
amount of leakage current (e.g. the switch may not be fully turned off). (3) The use of
bootstrapped clocking, which has added loading and possible reliability issues. (4) The switched-opamp
(SO) technique which is fully compatible with low-voltage submicron CMOS processes
but the operating speed limited due to slow transients from the opamp being switched off and on.
In this thesis, the Opamp-Reset Switching Technique (ORST) topology is proposed for
low-voltage operation. Instead of opamps being turned on and off as in the switched-opamp
technique, the sourcing amplifier is placed in the unity-gain reset configuration to provide reset
level at the output. In this way, high-speed operation is possible. The technique is applied to two
ADCs as examples of low-voltage design.
The first design is a 10-bit 25MSPS pipelined ADC using pseudo-differential structure. It
is fabricated in a 0.35-��m CMOS process. It operates at 1.4V and consumes 21mW of total power.
The second design is a two-stage algorithmic ADC with highly linear input sampling circuit. In
addition to the low-voltage design techniques used in the pipelined ADC, radix-based digital
calibration technique for multi-stage ADC is also proposed. The ADC uses a 0.18-��m CMOS
technology. It operates at 0.9V supply with total power consumption of 9mW. Experimental
results show that the proposed calibration technique reduces spurious free dynamic range from
47dB to 75dB and improves signal-to-noise and distortion ratio from 40dB to 55dB after
calibration. / Graduation date: 2003
| Identifer | oai:union.ndltd.org:ORGSU/oai:ir.library.oregonstate.edu:1957/31592 |
| Date | 15 November 2002 |
| Creators | Chang, Dong-Young |
| Contributors | Moon, Un-Ku |
| Source Sets | Oregon State University |
| Language | en_US |
| Detected Language | English |
| Type | Thesis/Dissertation |
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