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A subranging analog to digital converter using four bit pipepline

This thesis presents the design of a 10 bit Analog to
Digital Converter which consists of a 6 bit flash followed
by a 4 bit pipeline architecture. The total system is
described and the 4 bit pipeline is implemented on a bipolar
process.
The objective of this research is to provide an
alternative approach to high speed ADC designs and to
implement a pipeline ADC which samples at greater speeds
than those achieved with presently existing CMOS pipeline
designs.
This paper presents the complete architecture, the cell
design and simulated performance for each block in the
pipeline, and the measured results for the four bit pipeline
implementation. / Graduation date: 1993

Identiferoai:union.ndltd.org:ORGSU/oai:ir.library.oregonstate.edu:1957/36065
Date26 January 1993
CreatorsPress, Stephen E.
Source SetsOregon State University
Languageen_US
Detected LanguageEnglish
TypeThesis/Dissertation

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