Most present day implementations of delta-sigma modulators are discrete-time ones using switched-capacitor circuits. A resistor-capacitor (RC) implementation of a delta-sigma analog to digital converter (ADC) does not use switched capacitor (SC) technology. While SC implementation has the advantages of being discrete-time, no resistors used and improved stability control, RC implementation has the advantage of no switches being used (other than quantizer) and therefore a simpler circuit implementation. Continuous-time implementations can achieve lower thermal noise levels than switched capacitor modulators. Butterworth Multi-stage Noise Shaping (MASH) architecture is one of the promising architectures to implement in continuous-time domain. For a convenient design and quantization noise spectrum shaping of a delta sigma data converter, it's highly desirable for the Noise Transfer Function (NTF) to take the form of a high-pass filter. The MASH architecture was introduced to overcome stability problems commonly faced beyond a second order structure. Delta-sigma data converters are new converter designs that are preferred for integrated circuits and for high-resolution applications. It is highly desirable for the NTF of delta-sigma data converters to take the form of conventional highpass filters for convenient design purposes and shaping of the quantization noise spectrum. However, conventional delta-sigma architectures allow for only low orders and very low cutoff frequencies for such highpass filters, otherwise the converter becomes unstable. In previous projects it was found that a MASH implementation (each stage being second order) of a delta-sigma data converter where the NTF of each stage is a Butterworth highpass filter holds much promise. This current project is to accomplish RC implementation of fourth-order Butterworth MASH delta-sigma data converter. The circuit design procedure will be shown, starting with the desired NTF characteristics, and yielding the required parameters for the RC integrators with gains that are determined from the desired transfer function. The circuit simulation, yielding the bit stream frequency spectrum and the signal to noise ratio, will be based on Mentor Graphics Eldo SPICE simulations. The performance and characteristics of the circuit is fully analyzed and documented for a wide variety of variations and test conditions. / Thesis (M.S.)--Wichita State University, College of Engineering, Dept. of Electrical and Computer Engineering. / "August 2006." / Includes bibliographic references (leaves 41-43).
| Identifer | oai:union.ndltd.org:WICHITA/oai:soar.wichita.edu:10057/568 |
| Date | 08 1900 |
| Creators | Vijjapu, Sudheer |
| Contributors | Paarmann, Larry D. |
| Source Sets | Wichita State University |
| Language | en_US |
| Detected Language | English |
| Type | Thesis |
| Format | x, 51 leaves: ill., digital, PDF file., 339148 bytes, application/pdf |
| Rights | Copyright Sudheer Vijjapu, 2006. All rights reserved. |
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