<p>Accurate analytic models for the area, delay and power of NoC routers realized in FPGA technology are presented. Several router designs are explored, including the demultiplexer-multiplexer design, the broadcast-and-select design, a RAM-based design, and pipelined designs with arbitrary amounts of buffering. The analytic models are compared with extensive experimental results, and shown to be very accurate. Using these router models, accurate analytic models for the area, delay and power of graph-based and hypergraph-based NoC topologies realized in FPGAs are presented, including 2D Mesh, Torus, Binary Hypercube (BHC), Generalized Hypercube (GHC), and Hypermesh. Three traffic patterns are considered, (a) Random-Uniform traffic patterns, (b) traffic patterns in Bitonic sorting algorithm, and (c) traffic patterns in FFT parallel algorithm.</p> <p>The analytic models for NoCs are compared to extensive experimental results and shown to be very accurate, typically within 10%. Using these analytical models, architectural choices such as NoC topology, buffer sizing, crossbar switch design, and degree of pipelining can be explored analytically early in the design-space exploration process. It has been observed that an efficient and accurate early design process results in lower system costs, and in order to come up with feasible designs, early design-space exploration tools are essential.</p> <p>Early design-space exploration tools using analytic models are ideal, as they do not require the generation of detailed logic design in a hardware description language such as VHDL or Verilog. However, to date there are no analytic models for NoCs in FPGAs. This thesis addresses this problem. According to our analytic power models, in an FPGA environment with equal bisection bandwidth the 2D BHC outperforms the 2D Mesh and Torus significantly. For example under equivalent bisection bandwidth, when performing FFT computations in an FPGA environment the 2D BHC consumes 8% of the power of a 2D Mesh, and 15% of the power of a 2D Torus.</p> <p>Hypermeshes are based on the concept of hypergraphs, which consist of a set of nodes and a set of hyperedges, where the hyperedges represent low-latency switches. Under equivalent bisection bandwidth, 2D Hypermesh NoCs outperform the 2D Mesh and Torus significantly. To improve the performance of the Hypermesh, two new hyperedge designs are proposed. We propose the energy-area product as a design metric to compare the NoCs. The energy-area product reflects both the cost and performance design metrics. Our analysis indicates that the 2D Hypermesh NoCs generally have considerably lower area, energy, and energy-area product compared to the 2D Hypercubes. Under equal bisection bandwidth, the area usage of the 2D Hypermesh using the broadcast-and-select designs as the hyperedges uses 30% of the area of the GHC and 42% of the area of the BHC. The energy-area product of the 2D Hypermesh under the FFT algorithm is 9% of the GHC, and 29% of the BHC.</p> / Doctor of Philosophy (PhD)
| Identifer | oai:union.ndltd.org:mcmaster.ca/oai:macsphere.mcmaster.ca:11375/13329 |
| Date | 10 1900 |
| Creators | Binesh, Marvasti Mohammadreza |
| Contributors | Szymanski, Ted H., Electrical and Computer Engineering |
| Source Sets | McMaster University |
| Detected Language | English |
| Type | thesis |
Page generated in 0.0087 seconds