Return to search

Emulace CPU pro výuku asemblerů / A CPU Emulator for Course of Assembly Languages

The master thesis discusses the design of an emulator of a CPU architecture instruction set aimed at assembly languages course. While most of nowadays emulators are architecture specific, the emulator proposed in master thesis aims at education and better understanding of assembly languages. The emulator is not limited to a single CPU, but it easily allows defining a purpose-specific architecture and instruction set in order to perform operations upon it and to display its current state.

Identiferoai:union.ndltd.org:nusl.cz/oai:invenio.nusl.cz:236935
Date January 2011
CreatorsCharvát, Lukáš
ContributorsSamek, Jan, Smrčka, Aleš
PublisherVysoké učení technické v Brně. Fakulta informačních technologií
Source SetsCzech ETDs
LanguageCzech
Detected LanguageEnglish
Typeinfo:eu-repo/semantics/masterThesis
Rightsinfo:eu-repo/semantics/restrictedAccess

Page generated in 0.0016 seconds