Bibliography: leaves 158-167. / xvii, 173 leaves ; 30 cm. / Title page, contents and abstract only. The complete thesis in print form is available from the University Library. / Investigates two level logic synthesis of asynchronous circuits from signal transition graphs (STGs) under the inertial gate delay model and the well behaved environment. Focuses on design methodologies and hazard free implementations based on redundant logic where the inertial delay model does not help to avoid hazards. / Thesis (Ph.D.)--University of Adelaide, Dept. of Electrical and Electronic Engineering, 1997
| Identifer | oai:union.ndltd.org:ADTP/279891 |
| Date | January 1997 |
| Creators | Tabrizi, Nozar |
| Source Sets | Australiasian Digital Theses Program |
| Language | en_US |
| Detected Language | English |
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