Lee Chi-wai. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2002. / Includes bibliographical references (leaves 191-196). / Abstracts in English and Chinese. / Abstract of this thesis entitled: --- p.i / 摘要 --- p.iii / Acknowledgements --- p.v / Table of Contents --- p.vii / List of Tables --- p.x / List of Figures --- p.xi / Chapter Chapter1 --- Introduction --- p.1 / Chapter 1.1 --- Synchronous Design --- p.1 / Chapter 1.2 --- Asynchronous Design --- p.2 / Chapter 1.3 --- Discrete Cosine Transform --- p.4 / Chapter 1.4 --- Motivation --- p.5 / Chapter 1.5 --- Organization of the Thesis --- p.6 / Chapter Chapter2 --- Asynchronous Design Methodology --- p.7 / Chapter 2.1 --- Overview --- p.7 / Chapter 2.2 --- Background --- p.8 / Chapter 2.3 --- Past Designs --- p.10 / Chapter 2.4 --- Micropipeline --- p.12 / Chapter 2.5 --- New Asynchronous Architecture --- p.15 / Chapter Chapter3 --- DCT/IDCT Processor Design Methodology --- p.24 / Chapter 3.1 --- Overview --- p.24 / Chapter 3.2 --- Hardware Architecture --- p.25 / Chapter 3.3 --- DCT Algorithm --- p.26 / Chapter 3.4 --- Used Architecture and DCT Algorithm --- p.30 / Chapter 3.4.1 --- Implementation on Programmable DSP Processor --- p.31 / Chapter 3.4.2 --- Implementation on Dedicated Processor --- p.33 / Chapter Chapter4 --- New Techniques for Operating Dynamic Logic in Low Frequency --- p.36 / Chapter 4.1 --- Overview --- p.36 / Chapter 4.2 --- Background --- p.37 / Chapter 4.3 --- Traditional Technique --- p.39 / Chapter 4.4 --- New Technique - Refresh Control Circuit --- p.40 / Chapter 4.4.1 --- Principle --- p.41 / Chapter 4.4.2 --- Voltage Sensor --- p.42 / Chapter 4.4.3 --- Ring Oscillator --- p.43 / Chapter 4.4.4 --- "Counter, Latch and Comparator" --- p.46 / Chapter 4.4.5 --- Recalibrate Circuit --- p.47 / Chapter 4.4.6 --- Operation Monitoring Circuit --- p.48 / Chapter 4.4.7 --- Overall Circuit --- p.48 / Chapter Chapter5 --- DCT Implementation on Programmable DSP Processor --- p.51 / Chapter 5.1 --- Overview --- p.51 / Chapter 5.2 --- Processor Architecture --- p.52 / Chapter 5.2.1 --- Arithmetic Unit --- p.53 / Chapter 5.2.2 --- Switching Network --- p.56 / Chapter 5.2.3 --- FIFO Memory --- p.59 / Chapter 5.2.4 --- Instruction Memory --- p.60 / Chapter 5.3 --- Programming --- p.62 / Chapter 5.4 --- DCT Implementation --- p.63 / Chapter Chapter6 --- DCT Implementation on Dedicated DCT Processor --- p.66 / Chapter 6.1 --- Overview --- p.66 / Chapter 6.2 --- DCT Chip Architecture --- p.67 / Chapter 6.2.1 --- ID DCT Core --- p.68 / Chapter 6.2.1.1 --- Core Architecture --- p.74 / Chapter 6.2.1.2 --- Flow of Operation --- p.76 / Chapter 6.2.1.3 --- Data Replicator --- p.79 / Chapter 6.2.1.4 --- DCT Coefficients Memory --- p.80 / Chapter 6.2.2 --- Combination of IDCT to 1D DCT core --- p.82 / Chapter 6.2.3 --- Accuracy --- p.85 / Chapter 6.3 --- Transpose Memory --- p.87 / Chapter 6.3.1 --- Architecture --- p.89 / Chapter 6.3.2 --- Address Generator --- p.91 / Chapter 6.3.3 --- RAM Block --- p.94 / Chapter Chapter7 --- Results and Discussions --- p.97 / Chapter 7.1 --- Overview --- p.97 / Chapter 7.2 --- Refresh Control Circuit --- p.97 / Chapter 7.2.1 --- Implementation Results and Performance --- p.97 / Chapter 7.2.2 --- Discussion --- p.100 / Chapter 7.3 --- Programmable DSP Processor --- p.102 / Chapter 7.3.1 --- Implementation Results and Performance --- p.102 / Chapter 7.3.2 --- Discussion --- p.104 / Chapter 7.4 --- ID DCT/IDCT Core --- p.107 / Chapter 7.4.1 --- Simulation Results --- p.107 / Chapter 7.4.2 --- Measurement Results --- p.109 / Chapter 7.4.3 --- Discussion --- p.113 / Chapter 7.5 --- Transpose Memory --- p.122 / Chapter 7.5.1 --- Simulated Results --- p.122 / Chapter 7.5.2 --- Measurement Results --- p.123 / Chapter 7.5.3 --- Discussion --- p.126 / Chapter Chapter8 --- Conclusions --- p.130 / Appendix --- p.133 / Operations of switches in DCT implementation of programmable DSP processor --- p.133 / C Program for evaluating the error in DCT/IDCT core --- p.135 / Pin Assignments of the Programmable DSP Processor Chip --- p.142 / Pin Assignments of the 1D DCT/IDCT Core Chip --- p.144 / Pin Assignments of the Transpose Memory Chip --- p.147 / Chip microphotograph of the 1D DCT/IDCT core --- p.150 / Chip Microphotograph of the Transpose Memory --- p.151 / Measured Waveforms of 1D DCT/IDCT Chip --- p.152 / Measured Waveforms of Transpose Memory Chip --- p.156 / Schematics of Refresh Control Circuit --- p.158 / Schematics of Programmable DSP Processor --- p.164 / Schematics of 1D DCT/IDCT Core --- p.180 / Schematics of Transpose Memory --- p.187 / References --- p.191 / Design Libraries - CD-ROM --- p.197
| Identifer | oai:union.ndltd.org:cuhk.edu.hk/oai:cuhk-dr:cuhk_324007 |
| Date | January 2002 |
| Contributors | Lee, Chi-wai., Chinese University of Hong Kong Graduate School. Division of Electronic Engineering. |
| Source Sets | The Chinese University of Hong Kong |
| Language | English, Chinese |
| Detected Language | English |
| Type | Text, bibliography |
| Format | print, xiv, 197 leaves : ill. ; 30 cm. + 1 CD-ROM (4 3/4 in.) |
| Rights | Use of this resource is governed by the terms and conditions of the Creative Commons “Attribution-NonCommercial-NoDerivatives 4.0 International” License (http://creativecommons.org/licenses/by-nc-nd/4.0/) |
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