Most current methods used for the estimation of vehicular delay at intersections involve some form of manual data collection. These methods rely on statistical correlation to improve the accuracy of the delay estimates. In addition, most require significant data collection and reduction efforts.
This work presents the theory, design, and operation of a microprocessor-based system for the collection of vehicular delay data at intersections. The hardware design is described in detail including schematic diagrams of the microprocessor system and the associated interface circuitry. Documented software listings and flowcharts are provided as well as a description of the data collection and reduction processes.
A benefit/cost analysis was made based on the construction and operation of a prototype system. The system performance was evaluated both in the lab and through analysis of data collected in the field. Recommendations for further development of the device are presented as well as applications of the microprocessor to other forms of transportation and traffic engineering data. / M.S.
| Identifer | oai:union.ndltd.org:VTETD/oai:vtechworks.lib.vt.edu:10919/105995 |
| Date | January 1983 |
| Creators | Legere, Jay Francis |
| Contributors | Civil Engineering |
| Publisher | Virginia Polytechnic Institute and State University |
| Source Sets | Virginia Tech Theses and Dissertation |
| Language | English |
| Detected Language | English |
| Type | Thesis, Text |
| Format | x, 209 leaves, application/pdf, application/pdf |
| Rights | In Copyright, http://rightsstatements.org/vocab/InC/1.0/ |
| Relation | OCLC# 10185586 |
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