Return to search

Implementace umělé neuronové sítě do obvodu FPGA / FPGA implementation of artificial neural network

This master's thesis describes the design of effective working artificial neural network in FPGA Virtex-5 series with the maximum use of the possibility of parallelization. The theoretical part contains basic information on artificial neural networks, FPGA and VHDL. The practical part describes the used format of the variables, creating non-linear function, the principle of calculation the single layers, or the possibility of parameter settings generated artificial neural networks.

Identiferoai:union.ndltd.org:nusl.cz/oai:invenio.nusl.cz:219363
Date January 2011
CreatorsČermák, Justin
ContributorsŠteffan, Pavel, Bohrn, Marek
PublisherVysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií
Source SetsCzech ETDs
LanguageCzech
Detected LanguageEnglish
Typeinfo:eu-repo/semantics/masterThesis
Rightsinfo:eu-repo/semantics/restrictedAccess

Page generated in 0.0019 seconds