As the technology advances, the feature size of the modern integrated circuits (ICs) has decreased dramatically to nanometer amplitude. On one hand, the shrink brings benefits, such as high speed and low power consumption per transistor. On the other hand, it poses a threat to the reliable operation of the ICs by the increased radiation sensitivity, such as single event effects (SEEs). For example, in 2010, a commercial-off-the-shelf (COTS) BiCMOS DC/DC pulse width modulator (PWM) IC was observed to be sensitive to neutrons on terrestrial real-time applications, where negative 6-μs glitches were induced by the single event transient (SET) effects. As a result, a project was set up to comprehensively study the failure mechanisms with various test methodologies and to develop SET-tolerant circuits to mitigate the SET sensitivity.
First, the pulsed laser technique is adopted to perform the investigation on the SET response of the DC/DC PWM chip. A Ti:Sapphire single photon absorption (SPA) laser with different wavelengths and repetition rates is used as an irradiation source in this study. The sensitive devices in the chip are found to be the bandgap voltage reference circuit thanks to the well-controlled location information of the pulsed laser. The result is verified by comparing with the previous alpha particle and neutron testing data as well as circuit simulation using EDA tools. The root cause for the sensitivity is also acquired by analyzing the circuit. The temperature is also varied to study the effect of the temperature-induced quiescent point shift on the SET sensitivity of the chip. The experimental results show that the quiescent point shifts have different impacts on SET sensitivities due to the different structures and positions of the circuitries. After that, heavy ions, protons, and the pulsed X-ray are used as irradiation sources to further study the SET response of the DC/DC chip. The heavy ion and pulsed laser data are correlated to each other. And the equivalent LETs for laser with wavelengths of 750 nm, 800 nm, 850 nm and 920 nm are acquired. This conclusion can be used to obtain the equivalent heavy ion cross section of any area in a chip by using the pulsed laser technique, which will facilitate the SET testing procedure dramatically. The proton and heavy ion data are also correlated to each other based on a rectangular parallel piped (RPP) model, which gives convenience in Soft Error Rate (SER) estimation. The potential application of pulsed X-ray technique in SET field is also investigated. It is capable of generating similar results with those of heavy ion and pulsed laser testing. Both the advantages and disadvantages of this technique are explained. This provides an alternative choice for the SET testing in the future. Finally, the bandgap voltage reference circuit in the DC/DC PWM is redesigned and fabricated in bulk CMOS 130nm technology and a SET hardened bandgap circuit is proposed and investigated. The CMOS substrate PNP transistor is much less sensitive to SETs than the BiCMOS NPN transistor according to the pulsed laser test results. The reason is analyzed to be the different fabrication processes of the two technologies. The laser test results also indicate that the SET hardened bandgap circuit can mitigate the SET amplitude dramatically, which is consistent with the SPICE simulation results. These researches provide more understandings on the design of SET hardened bandgap voltage reference circuit.
| Identifer | oai:union.ndltd.org:USASK/oai:ecommons.usask.ca:10388/ETD-2015-02-1953 |
| Date | 2015 February 1900 |
| Contributors | Chen, Li |
| Source Sets | University of Saskatchewan Library |
| Language | English |
| Detected Language | English |
| Type | text, thesis |
Page generated in 0.002 seconds