With the scaling of technology nodes, the speed performance
of microprocessors has rapidly improved but the scaling of off-chip
input/output (I/O) bandwidth is limited by physical pin resources
and interconnect technologies. In order to reduce the performance
gaps, new interface techniques have emerged and the marketplace has
moved towards higher levels of integration with system on a chip
(SoC) implementations. The advent of new techniques, however, has
led to new challenges on the semiconductor and automated test
equipment (ATE) industries. The relatively slow growing ATE
technology comparing to I/O speeds especially intensifies
manufacturing test issues. Testing high speed I/O timing parameters
requires expensive high performance test equipment with high
accuracy and resolution. The requirements increase integrated
circuit (IC) manufacturing costs and thus test issues have become
critical.
This thesis focuses on on-chip test methods to improve test accuracy
and reduce test costs for high speed double data rate (DDR) memory
I/Os using source synchronous clocking. For testing the I/O timing
parameters, a phase interpolator based on-chip timing sampler using
a cycle-by-cycle control method was developed. This circuit
generates data and clock patterns and controls the time delay
between data and clock to detect the timing mismatch which indicates
timing degradations. The on-chip timing sampler was implemented as a
built-in self test (BIST) circuit for low-cost parametric timing
measurements. The BIST scheme was fabricated with a 0.18-um CMOS
process technology. Using the static and dynamic modes, measurement
results are obtained for the I/O timing parameters such as the setup
and hold times, input voltage-level variations tolerances, duty
distortion tolerances and data skews. Moreover, a delay mismatch
measurement method was developed to improve measurement accuracy
using a simple control circuit. This delay mismatch detector
measures timing mismatches between data and clock paths and then the
timing mismatches are converted to timing specifications. This
scheme is also implemented along with analog to digital converter
(ADC) to collect digital test results supporting low-cost
system-level tests. Thus, the low-frequency test results show that
our on-chip measurement techniques provide an attractive low-cost
solution and is effectively applied for testing high speed source
synchronous systems. / text
| Identifer | oai:union.ndltd.org:UTEXAS/oai:repositories.lib.utexas.edu:2152/19455 |
| Date | 14 February 2013 |
| Creators | Kim, Hyun Jin, doctor of electrical and computer engineering |
| Source Sets | University of Texas |
| Language | en_US |
| Detected Language | English |
| Format | application/pdf |
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