The first topic of this thesis is a novel voltage tripler using 4 clocks with different phases. Both the positive and negative polarities of the voltage are generated to serve as the boosted voltage and the back bias voltage. The proposed design is carried out by pass transistors and switched capacitors.
The second topic is a low-power discrete cosine transform (DCT) processor. It is suitable for portable applications. The number of clock cycles needed for processing an 8¡Ñ8 block of pixels is increased, but the chip area is reduced. The reduction of the chip area leads to the reduction of the power dissipation.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-1102102-001654 |
| Date | 02 November 2002 |
| Creators | Kuo, Ting-Wan |
| Contributors | Chi-Feng Wu, Chua-Chin Wang, Shie-Jue Lee |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1102102-001654 |
| Rights | not_available, Copyright information available at source archive |
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