In this thesis, a novel low power multiplier design is introduced. We utilize the bypassing logic to construct a multiplier based on ripple carry array to minimize the switching activities rather than carry save array for the low power requirement and tree structure to enhance the performance. The advantage of using the bypassing logic in the ripple carry array multiplier is that it can use less extra hardware and achieve more power saving compared with conventional multipliers. The design of our circuit uses the standard TSMC 0.18um technology and simulates with Hspice. According to the simulation results, the proposed design can obtain power saving around 15% more than conventional multipliers, although it must occupy larger area.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0722106-190715 |
| Date | 22 July 2006 |
| Creators | Chou, Chi-Wen |
| Contributors | Shiann-Rong Kuang, Huei-Yung Lin, Shen-Fu Hsiao, Ko-Chi Kuo |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | English |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0722106-190715 |
| Rights | not_available, Copyright information available at source archive |
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